The transistor is no longer the operative limit on AI hardware. The binding constraint sits one step later in the process: the physical integration of logic and memory that turns a finished die into a working accelerator. Advanced packaging and high-bandwidth memory (HBM) are now the chokepoints, and both are more concentrated, slower to expand and more exposed to geography than the wafer fabrication that dominates most discussion of the semiconductor supply chain.
The Constraint Moved Downstream
A frontier AI accelerator needs three inputs: an advanced logic die, stacks of HBM, and a 2.5D packaging process that places the two side by side on a silicon interposer. Epoch AI estimates that the four largest AI chip designers consumed roughly 90 percent of global advanced packaging and HBM supply in 2025, while AI chips took only about 12 percent of advanced logic supply, because logic fabrication also serves smartphones, laptops and vehicles.1
That ratio is the core of the argument. A logic wafer can be fabricated on schedule and still sit idle if no packaging slot or memory stack is available to complete it. When nearly all of an input's output flows to one end market, that market's growth rate is capped by the input's capacity, not by demand.
The takeaway: the pace of AI hardware deployment is now set by the integration layer, and capacity added at the wafer stage does not relieve it.
Concentration at Every Critical Node
The market structure of this layer is unusually narrow. A July 2026 working paper on arXiv measures concentration across the AI input stack on the Herfindahl-Hirschman Index, the same scale U.S. antitrust agencies use, where 1,800 marks a highly concentrated market. It scores high-bandwidth memory, a three-firm market, at 4,174, and advanced packaging, where a single firm performs roughly 90 percent of the work current accelerators require, at 8,100.2 The same paper reports that 92 percent of leading-edge logic fabrication sits in one geography, Taiwan, and that five firms supply about 70 percent of wafer-fabrication equipment.
The paper's broader finding is a gradient: concentration is lowest at the model and cloud layers, where regulatory attention is heaviest, and rises steeply toward the physical inputs, where attention is thin.2 For anyone analyzing the hardware layer, that means scarcity and pricing power are held by a small number of producers at each critical step, with little near-term prospect of new entrants.
The takeaway: the inputs that set the pace of AI are among the most concentrated markets in the industrial economy.
Memory Has Become the Expensive Part
High-bandwidth memory has moved from a specialty product to the scarcest component in the accelerator. Seoul Economic Daily reported on October 1, 2026 that TrendForce projects HBM average selling prices will rise 121 percent in 2027, citing a persistent supply shortage and a shift toward more expensive next-generation stacks. The same report notes that producers have already contracted most of their 2027 HBM output at prices above 2026 levels.3
Supply is slow to respond for technical reasons. HBM is built by stacking multiple memory dies connected with through-silicon vias, then testing and integrating the stack with the processor, and yield losses compound at each step. Adding capacity means converting cleanroom space and qualifying equipment, which diverts output from conventional DRAM and tightens that market in turn.
The takeaway: memory economics have split in two. HBM behaves like a differentiated, supply-constrained product with contracted demand a year out; conventional memory absorbs the cost of the capacity being pulled away from it.
Packaging Capacity Lags Demand
The packaging bottleneck has proved more persistent than the memory one. TrendForce reported on April 30, 2026 that 2.5D packaging has been undersupplied since 2023, and that the shortage has spread upstream to production equipment and downstream to substrates and packaging materials. It expects the severe shortage to begin easing only slightly by 2027, as the dominant provider expands 2.5D capacity by more than 60 percent and some orders spill over to outsourced assembly and test providers.4
Demand is not standing still while capacity is built. Business Insider reported on October 30, 2026 that the five largest hyperscale cloud and technology spenders are on track for between $803 billion and $828 billion of capital expenditure in calendar 2026, a figure that covers all capital spending but that executives attribute mainly to AI infrastructure, with further increases signaled for 2027.5 Each generation of accelerator also uses more packaging area and more memory per chip, so unit demand for the integration layer grows faster than unit demand for chips.
The takeaway: a 60 percent capacity expansion against that demand curve narrows the gap rather than closing it, which keeps the integration layer as the pacing constraint into 2027.
Geography and Policy
The concentration is also geographic. Advanced packaging capacity is overwhelmingly located in Taiwan, and HBM production is concentrated in South Korea, so the two scarcest inputs in AI hardware are produced in a corridor at the center of the most consequential geopolitical tension of the decade.
Policy has followed the bottleneck downstream. The Bureau of Industry and Security's December 5, 2024 interim final rule added new export controls on certain high-bandwidth memory, alongside new controls on semiconductor manufacturing equipment and new foreign direct product rules.6 Earlier controls focused on lithography and leading-edge logic; this rule treats the memory stack itself as a strategic item. The policy architecture now aims to restrict AI hardware capability by controlling the integration inputs, not only the chip.
The takeaway: the bottleneck is now a national-security variable as well as a commercial one, and policy decisions on either side of it can move supply faster than any capacity plan.
Where the Thesis Lands
In our view, advanced packaging and high-bandwidth memory, not transistor density, now set the pace at which AI compute can be deployed. The constraint is technical: capacity takes years of qualification, specialized tooling and cleanroom space that cannot be repurposed quickly, and the evidence above shows demand absorbing nearly all of it.
Three developments would challenge the thesis: a sustained slowdown in data center construction that pulls demand below current capital spending plans; faster qualification of alternative packaging approaches that loosens the current single-provider concentration; or a capable domestic Chinese packaging and memory base that blunts the effect of export controls. The first runs against hyperscaler spending guidance reported in late October. The second depends on alternative processes that TrendForce describes as gaining traction but not yet at scale.4 The third is the explicit target of the December 2024 controls, which is itself evidence that policymakers regard it as a credible medium-term risk.
The transistor was never the whole story. The integration layer that makes a chip usable is where the scarcity in AI hardware now sits.
Footnotes
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Epoch AI, "Advanced packaging and HBM, not logic dies, were the bottlenecks on AI chip production in 2025," March 12, 2026 ↩
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arXiv, "Artificial Intelligence: Supply-Chain Chokepoints and the Reach of Industrial Policy," July 2026 ↩ ↩2
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Seoul Economic Daily, "HBM Prices to More Than Double Next Year as Shortage Persists," October 1, 2026 ↩
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TrendForce via I-Connect007, "AI Competition Turns into a Supply Chain Arms Race, Tightening Advanced Packaging and 3nm Capacity," April 30, 2026 ↩ ↩2
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Business Insider (republished on hl.co.uk), "AI hyperscalers are expected to finish the year spending a whopping $828 billion on capex," October 30, 2026 ↩
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Federal Register, Bureau of Industry and Security, "Foreign-Produced Direct Product Rule Additions, and Refinements to Controls for Advanced Computing and Semiconductor Manufacturing Items," December 5, 2024 ↩